1. Field of Invention
The present invention relates to a test circuit and method for a communication system in which serial data is transmitted and received at very high speed.
2. Description of Related Art
A transceiver is an indispensable device for the realization of a high-speed data communication system. The transceiver converts low-speed parallel data into high-speed serial data and then transmits the serial data through a transmission path comprising an optical fiber. Further, the transceiver receives high-speed serial data, detects a point of change in the serial data to generate a recovery clock, and then converts the serial data into low-speed parallel data synchronously with the recovery clock.
FIG. 9 is a schematic diagram showing a configuration of an example of 10GBASE-X PMA (Physical Medium Attachment) (PMA) defined by IEEE P802.3ae.
A PMA 60 includes four transceivers 62. Each transceiver 62 comprises a transmitter unit 64 for converting parallel data into serial data and then transmitting the serial data, and a receiver unit 66 for receiving serial data and then converting the received data into parallel data.
In each transceiver 62, the transmitter unit 64 converts 10-bit wide parallel data transmitted at 312.5 Mbps (megabit/second) into 1-bit wide differential serial data to be transmitted at 3.125 Gbps (gigabit/second), and then transmits the converted data (3.125-Gbps data output). The receiver unit 66 receives 1-bit wide differential serial data at 3.125 Gbps (3.125-Gbps data input) and then converts the received data into 10-bit wide parallel data (parallel output) to be transmitted at 312.5 Mbps synchronously with a recovery clock generated based on the serial data.
Testing is the most important challenge in the implementation of the foregoing transceivers 62 on a semiconductor chip. The reason is as follows: an operation performed at actual operating speed cannot be confirmed in a low-speed function test such as a conventional LSI test. Accordingly, whether a semiconductor chip has been produced in normal fashion cannot be confirmed. In addition, a tester capable of handling a data signal transmitted or received at a high speed of 3.125 Gbps is very expensive, resulting in an increase of the test cost.
In designing the transceiver 62, a Built-In-Self-Test (BIST) circuit for performing a self-test, generally called a loopback test, at actual operating speed is built in each transceiver.
With the PMA 60 shown in FIG. 9, a test signal generation unit 68 for generating test parallel data is arranged near a parallel data input of the transmitter unit 64 in each transceiver 62. In the normal operation, parallel data supplied from the outside of the chip is input to the transmitter unit 64 through a multiplexer 70. In the test operation, test parallel data that is generated by the test signal generation unit 68 is input to the transmitter unit 64 through the multiplexer 70. In the transmitter unit 64, the input parallel data is converted into serial data and is then transmitted.
In the normal operation, serial data supplied from the outside of the chip is input to the receiver unit 66 through a multiplexer 72. In the test operation, serial data output from the corresponding transmitter unit 64 is input to the receiver unit 66 through the multiplexer 72. An error detection unit 74 is disposed near a parallel data output of the receiver unit 66. In the test operation, the error detection unit 74 detects an error in the parallel data converted by the receiver unit 66.
In other words, in the test operation, the test signal generation unit 68 generates test parallel data. The transmitter unit 64 converts the test parallel data into serial data and then transmits the data. The receiver unit 66 receives the serial data output from the transmitter unit 64 through the multiplexer 72 and then converts the serial data into parallel data. The error detection unit 74 detects whether the converted parallel data has included an error.
When the BIST circuit is used, the transmitter unit 64 and the receiver unit 66 can be simultaneously tested at the actual operating speed.
In the implementation of the transceivers 62 on one semiconductor chip, for example, the following arrangement is made in some cases. As shown in FIG. 10, the receiver units 66 are disposed in the left portion of the chip, the transmitter units 64 are arranged in the right portion thereof, and a signal received by each receiver unit 66 is supplied to the corresponding transmitter unit 64 through a user logic 76. The reason is as follows where a system is constructed, for example, having a plurality of chips each including the transceivers 62, the foregoing arrangement with the least waste is obtained in consideration of wiring of data signal lines in board designing.
In order to realize the arrangement shown in FIG. 10, it is necessary to arrange each receiver unit 66 and the corresponding transmitter unit 64 separately from each other. Therefore, when the conventional BIST circuit as shown in FIG. 9 is built in each transceiver, each receiver unit 66 requires a dummy transmitter unit 78 for test purpose and each transmitter unit 64 needs a dummy receiver unit 80 for test purpose. Accordingly, the chip area increases, resulting in an increase in the cost.